Modeling Process Variability in Scaled CMOS Technology

  • Authors:
  • Samar K. Saha

  • Affiliations:
  • University of Colorado at Colorado Springs

  • Venue:
  • IEEE Design & Test
  • Year:
  • 2010

Quantified Score

Hi-index 0.00

Visualization

Abstract

Editor's note:Process variability has become a critical issue in scaled CMOS design. This article provides a comprehensive view on the predominant variation sources in sub–90-nm devices, their impact on device and circuit performance, and various modeling approaches for statistical circuit analysis.—Yu Cao, Arizona State University