Circuit bipartitioning using genetic algorithm

Authors:
Jong-Pil Kim;Byung-Ro Moon
Affiliations:
School of Computer Science and Engineering, Seoul National University, Seoul, Korea;School of Computer Science and Engineering, Seoul National University, Seoul, Korea
Venue:
GECCO'03 Proceedings of the 2003 international conference on Genetic and evolutionary computation: PartII
Year:
2003

Citing 3
Cited 0

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Abstract

In this paper, we propose a hybrid genetic algorithm for partitioning a VLSI circuit graph into two disjoint graphs of minimum cut size. The algorithm includes a local optimization heuristic which is a modification of Fiduccia-Matheses algorithm. Using well-known benchmarks (including ACM/SIGDA benchmarks), the combination of genetic algorithm and the local heuristic outperformed hMetis [3], a representative circuit partitioning algorithm.