Validating timed UML models by simulation and verification
International Journal on Software Tools for Technology Transfer (STTT) - Special Section on Specification and Validation of Models of Real Time and Embedded Systems with UML
Simulink timed models for program verification
Theories of Programming and Formal Methods
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This paper presents an overview on the outcomes of the workshop MARTES on Modelling and Analysis of Real Time and Embedded Systems that has taken place for the second time in association with the MoDELS/UML 2006 conference. Important themes discussed at this workshop concerned (1) tools for analysis and model transformation and (2) concepts for modelling quantitative aspects with the perspective of analysis.