Validating timed UML models by simulation and verification

  • Authors:
  • Iulian Ober;Susanne Graf;Ileana Ober

  • Affiliations:
  • VERIMAG 2, av. de Vignate, 38610, Gières, France;VERIMAG 2, av. de Vignate, 38610, Gières, France;VERIMAG 2, av. de Vignate, 38610, Gières, France

  • Venue:
  • International Journal on Software Tools for Technology Transfer (STTT) - Special Section on Specification and Validation of Models of Real Time and Embedded Systems with UML
  • Year:
  • 2006

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Abstract

This paper presents a technique and a tool for model-checking operational (design level) UML models based on a mapping to a model of communicating extended timed automata. The target language of the mapping is the IF format, for which existing model-checking and simulation tools can be used. Our approach takes into consideration most of the structural and behavioural features of UML, including object-oriented aspects. It handles the combination of operations, state machines, inheritance and polymorphism, with a particular semantic profile for communication and concurrency. We adopt a UML profile that includes extensions for expressing timing. The breadth of concepts covered by our mapping is an important point, as many previous approaches for applying formal validation to UML put much stronger limitations on the considered models. For expressing properties about models, a formalism called UML observers is defined in this paper. Observers reuse existing concepts like classes and state machines, and they allow expressing a significant class of linear temporal properties. The approach is implemented in a tool that imports UML models from an XMI repository, thus supporting several editors like Rational Rose, Rhapsody or Argo. The generated IF models may be simulated and verified via an interface that presents feedback in the vocabulary of the original UML model.