Efficient Büchi Automata from LTL Formulae
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
From PSL to NBA: a Modular Symbolic Encoding
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Resets vs. aborts in linear temporal logic
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Symbolic implementation of alternating automata
CIAA'06 Proceedings of the 11th international conference on Implementation and Application of Automata
Bounded model checking for weak alternating büchi automata
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Incremental and complete bounded model checking for full PLTL
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Symbolic systems, explicit properties: on hybrid approaches for LTL symbolic model checking
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
PSL model checking and run-time verification via testers
FM'06 Proceedings of the 14th international conference on Formal Methods
Formal Methods in System Design
Boolean abstraction for temporal logic satisfiability
CAV'07 Proceedings of the 19th international conference on Computer aided verification
A multi-encoding approach for LTL symbolic satisfiability checking
FM'11 Proceedings of the 17th international conference on Formal methods
| Hi-index | 0.00 |
The IEEE standard Property Specification Language (PSL) allows to express all ω-regular properties mixing Linear Temporal Logic (LTL) with Sequential Extended Regular Expressions (SEREs), and is increasingly used in many phases of the hardware design cycle, from specification to verification. In recent works, we propose a modular and symbolic PSL compilation that is extremely fast in conversion time and outperforms by several orders of magnitude translators based on the explicit construction and minimization of automata. Unfortunately, our approach creates rather redundant automata, which result in a penalty in verification time. In this paper, we propose a set of syntactic simplifications that enable to significantly improve the verification time without paying the price of automata simplifications. A thorough experimental analysis over large sets of paradigmatic properties shows that our approach drastically reduces the overall verification time.