Impact of Deep Submicron Technology on Dependability of VLSI Circuits
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
Fault Containment and Error Detection in the Time-Triggered Architecture
ISADS '03 Proceedings of the The Sixth International Symposium on Autonomous Decentralized Systems (ISADS'03)
Compositional Design of RT Systems: A Conceptual Basis for Specification of Linking Interfaces
ISORC '03 Proceedings of the Sixth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing
The Time-Triggered Ethernet (TTE) Design
ISORC '05 Proceedings of the Eighth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing
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DECOS (Dependable Components and Systems) is an EU-funded integrated research project (IP) with the goal to develop a framework and an associated design methodology for the component-based design of dependable embedded systems. The core of DECOS is based on the Time-Triggered Architecture (TTA), a distributed architecture for high-dependability real-time applications. In the first part of this paper the design flow of DECOS from the Platform Independent Model (PIM) to the Platform Specific Model (PSM) is discussed and the DECOS execution environment is introduced. In the second part the fault-tolerance mechanisms of DECOS are explained. After a deliberation of the fault hypothesis, the support for the implementation of triple-modular redundancy (TMR) is presented.