Integrating high-level optimizations in a production compiler: design and implementation experience

Authors:
Somnath Ghosh;Abhay Kanhere;Rakesh Krishnaiyer;Dattatraya Kulkarni;Wei Li;Chu-Cheow Lim;John Ng
Affiliations:
Intel® Compiler Laboratory, Intel Corporation, Santa Clara, CA;Intel® Compiler Laboratory, Intel Corporation, Santa Clara, CA;Intel® Compiler Laboratory, Intel Corporation, Santa Clara, CA;Intel® Compiler Laboratory, Intel Corporation, Santa Clara, CA;Intel® Compiler Laboratory, Intel Corporation, Santa Clara, CA;Intel® Compiler Laboratory, Intel Corporation, Santa Clara, CA;Intel® Compiler Laboratory, Intel Corporation, Santa Clara, CA
Venue:
CC'03 Proceedings of the 12th international conference on Compiler construction
Year:
2003

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Abstract

The High-Level Optimizer (HLO) is a key part of the compiler technology that enabled Itanium™ and Itanium™2 processors deliver leading floating-point performance at their introduction. In this paper, we discuss the design and implementation experience in integrating diverse optimizations in the HLO module. In particular, we describe decisions made in the design of HLO targeting Itanium processor family. We provide empirical data to validate the design decisions. Since HLO was implemented in a production compiler, we made certain engineering trade-offs. We discuss these trade-offs and outline key learning derived from our experience.