JCIT Proceedings of the fifth Jerusalem conference on Information technology
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Symbolic reachability analysis of FIFO-channel systems with nonregular sets of configurations
Theoretical Computer Science
Symbolic model checking with rich assertional languages
Theoretical Computer Science
Regular Model Checking Made Simple and Efficient
CONCUR '02 Proceedings of the 13th International Conference on Concurrency Theory
How to Compose Presburger-Accelerations: Applications to Broadcast Protocols
FST TCS '02 Proceedings of the 22nd Conference Kanpur on Foundations of Software Technology and Theoretical Computer Science
Verifying Systems with Infinite but Regular State Spaces
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Symbolic Techniques for Parametric Reasoning about Counter and Clock Systems
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Liveness and Acceleration in Parameterized Verification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Liveness with (0, 1, infty)-Counter Abstraction
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Symbolic Verification with Periodic Sets
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Multiple Counters Automata, Safety Analysis and Presburger Arithmetic
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Using Forward Reachability Analysis for Verification of Lossy Channel Systems
Formal Methods in System Design
Regular Model Checking Using Inference of Regular Languages
Electronic Notes in Theoretical Computer Science (ENTCS)
Regular model checking without transducers (on efficient verification of parameterized systems)
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
Flat acceleration in symbolic model checking
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Liveness by invisible invariants
FORTE'06 Proceedings of the 26th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Proving liveness by backwards reachability
CONCUR'06 Proceedings of the 17th international conference on Concurrency Theory
Fair Model Checking with Process Counter Abstraction
FM '09 Proceedings of the 2nd World Congress on Formal Methods
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Regular model checking is a form of symbolic model checking technique for systems whose states can be represented as finite words over a finite alphabet, where regular sets are used as symbolic representation. A major problem in symbolic model checking of parameterized and infinite-state systems is that fixpoint computations to generate the set of reachable states or the set of reachable loops do not terminate in general. Therefore, acceleration techniques have been developed, which calculate the effect of arbitrarily long sequences of transitions generated by some action. We present a systematic method for using acceleration in regular model checking, for the case where each transition changes at most one position in the word; this includes many parameterized algorithms and algorithms on data structures. The method extracts a maximal (in a certain sense) set of actions from a transition relation. These actions, and systematically obtained compositions of them, are accelerated to speed up a fixpoint computation. The extraction can be done on any representation of the transition relation, e.g., as a union of actions or as a single monolithic transducer. Using this approach, we are for the first time able to verify completely automatically both safety and absence of starvation properties for a collection of parameterized synchronization protocols from the literature; for some protocols, we obtain significant improvements in verification time. The results show that symbolic state-space exploration, without using abstractions, is a viable alternative for verification of parameterized systems with a linear topology.