Model checking memoryful linear-time logics over one-counter automata

  • Authors:
  • Stéphane Demri;Ranko Lazi;Arnaud Sangnier

  • Affiliations:
  • LSV, ENS Cachan, CNRS, INRIA Saclay IdF, F-94235 Cachan, cedex, France;Department of Computer Science, University of Warwick, UK;LSV, ENS Cachan, CNRS & EDF R&D, France

  • Venue:
  • Theoretical Computer Science
  • Year:
  • 2010

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Abstract

We study complexity of the model-checking problems for LTL with registers (also known as freeze LTL and written LTL"^@7) and for first-order logic with data equality tests (written FO^(~,