Increasing the Locality of Iterative Methods and Its Application to the Simulation of Semiconductor Devices

  • Authors:
  • J.C. Pichel;D.B. Heras;J.C. Cabaleiro;A.J. García-Loureiro;F.F. Rivera

  • Affiliations:
  • GALICIA SUPERCOMPUTING CENTER (CESGA), AVENIDA DE VIGO,S/N CAMPUS SUR, 15705 SANTIAGO DE COMPOSTELA, A CORUÑA, SPAIN;ELECTRONICS AND COMPUTING DEPARTMENT, UNIVERSIDADE DESANTIAGO DE COMPOSTELA, RUA CONGA 1, 15704 SANTIAGO DE COMPOSTELA, SPAIN,;ELECTRONICS AND COMPUTING DEPARTMENT, UNIVERSIDADE DESANTIAGO DE COMPOSTELA, RUA CONGA 1, 15704 SANTIAGO DE COMPOSTELA, SPAIN,;ELECTRONICS AND COMPUTING DEPARTMENT, UNIVERSIDADE DESANTIAGO DE COMPOSTELA, RUA CONGA 1, 15704 SANTIAGO DE COMPOSTELA, SPAIN,;ELECTRONICS AND COMPUTING DEPARTMENT, UNIVERSIDADE DESANTIAGO DE COMPOSTELA, RUA CONGA 1, 15704 SANTIAGO DE COMPOSTELA, SPAIN,

  • Venue:
  • International Journal of High Performance Computing Applications
  • Year:
  • 2010

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Abstract

Irregular codes are present in many scientific applications, such as finite element simulations. In these simulations the solution of large sparse linear equation systems is required, which are often solved using iterative methods. The main kernel of the iterative methods is the sparse matrixâ聙聰vector multiplication which frequently demands irregular data accesses. Therefore, techniques that increase the performance of this operation will have a great impact on the global performance of the iterative method and, as a consequence, on the simulations. In this paper a technique for improving the locality of sparse matrix codes is presented. The technique consists of reorganizing the data guided by a locality model instead of restructuring the code or changing the sparse matrix storage format. We have applied our proposal to different iterative methods provided by two standard numerical libraries. Results show an impact on the overall performance of the considered iterative method due to the increase in the locality of the sparse matrixâ聙聰vector product. Noticeable reductions in the execution time have been achieved both in sequential and in parallel executions. This positive behavior allows the reordering technique to be successfully applied to real problems. We have focused on the simulation of semiconductor devices and in particular on the BIPS3D simulator. The technique was integrated into the simulator. Both sequential and parallel executions have been analyzed extensively in this paper. Noticeable reductions in the execution time required by the simulations are observed when using our reordered matrices in comparison with the original simulator.