A hardware peripheral for Java bytecodes translation acceleration

Authors:
Isidoros Sideris;Nikos Moshopoulos;Kiamal Pekmestzi
Affiliations:
National Technical University of Athens, Athens, Greece;National Technical University of Athens, Athens, Greece;National Technical University of Athens, Athens, Greece
Venue:
Proceedings of the 2010 ACM Symposium on Applied Computing
Year:
2010

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Abstract

Java has gained great popularity in a wide range of applications. Just-in-time compilation is crucial for providing efficient execution of Java programs, but it is generally a hard task, not suited for embedded systems. This paper presents a hardware acceleration unit for efficient execution of JIT translation in embedded SoCs. The translation is limited to only first level optimizations, which include translation of Java bytecodes to native RISC instructions (stack folding). For experimentation, we developed a SoC with ARM7TDMI processor. In a f 80nm ASIC technology and 80MHz clock, we measured a speed up of up to 4 times over the software only JIT translation.