A fully integrated low-power 5-GHz CMOS RF receiver for WLAN applications
Proceedings of the 5th International Conference on Ubiquitous Information Management and Communication
Power-efficient analog design based on the class AB super source follower
International Journal of Circuit Theory and Applications
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A low-power CMOS receiver baseband analog (BBA) circuit based on alternating filter and gain stage is reported. For the given specifications of the BBA block, optimum allocation of the gain, input-referred third-order intercept point (IIP3), and noise figure (NF) of each block is performed to minimize current consumption. The fully integrated receiver BBA chain is fabricated in 0.18µm CMOS technology and IIP3 of 30 dBm with a maximum gain of 59 dB and NF of 31 dB are obtained at 3.6 mW power consumption. Copyright © 2008 John Wiley & Sons, Ltd.