FPGA implementation of an adaptive stochastic neural model

Authors:
Giuliano Grossi;Federico Pedersini
Affiliations:
Dipartimento di Scienze dell'Informazione, Università degli Studi di Milano, Milano, Italy;Dipartimento di Scienze dell'Informazione, Università degli Studi di Milano, Milano, Italy
Venue:
ICANN'07 Proceedings of the 17th international conference on Artificial neural networks
Year:
2007

Citing 3
Cited 1

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Computers and Intractability: A Guide to the Theory of NP-Completeness
Pseudo-boolean optimization

Discrete Applied Mathematics
A discrete adaptive stochastic neural model for constrained optimization

ICANN'06 Proceedings of the 16th international conference on Artificial Neural Networks - Volume Part I

2008 Special Issue: FPGA implementation of a stochastic neural network for monotonic pseudo-Boolean optimization

Neural Networks

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Abstract

In this paper a FPGA implementation of a novel neural stochastic model for solving constrained NP-hard problems is proposed and developed. The hardware implementation allows to obtain high computation speed by exploiting parallelism, as the neuron update and the constraint violation check phases can be performed simultaneously. The neural system has been tested on random and benchmark graphs, showing good performance with respect to the same heuristic for the same problems. Furthermore, the computational speed of the FPGA implementation has been measured and compared to software implementation. The developed architecture features dramatically faster computations with respect to the software implementation, even adopting a low-cost FPGA chip.