Implementation and evaluation of the mechanisms for low latency communication on DIMMnet-2

Authors:
Yasuo Miyabe;Akira Kitamura;Yoshihiro Hamada;Tomotaka Miyasiro;Tetsu Izawa;Noboru Tanabe;Hironori Nakajo;Hideharu Amano
Affiliations:
Faculty of Science and Technology Keio University, Yokohama, Japan;Faculty of Science and Technology Keio University, Yokohama, Japan;Tokyo University of Agriculture and Technology;Faculty of Science and Technology Keio University, Yokohama, Japan;Faculty of Science and Technology Keio University, Yokohama, Japan;Corporate Research and Development Center, Toshiba;Tokyo University of Agriculture and Technology;Faculty of Science and Technology Keio University, Yokohama, Japan
Venue:
ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
Year:
2005

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Abstract

DIMMnet-2 is a network interface for PC cluster, plugged into a DIMM slot. Connecting network interface into commonly used memory bus reduces the cost of building PC cluster compared with using expensive machines with recent high performance I/O bus like PCIX. Moreover, low latency communication from the host CPU can be achieved. In this paper, implementation of the mechanisms for low latency communication on the DIMMnet-2 prototype board by making the best use of the memory slot is shown. Its latency for 4 Bytes data transfer is only 1.4 µs which is lower than those of InfiniBand and QsNET II on condition those host processes are Intel Xeon.