Performance evaluation on low-latency Communication mechanism of DIMMnet-2

Authors:
Akira Kitamura;Yasuo Miyabe;Tomotaka Miyashiro;Noboru Tanabe;Hironori Nakajo;Hideharu Amano
Affiliations:
Faculty of Science and Technology Keio University, Kohoku-ku, Yokohama, Japan;Faculty of Science and Technology Keio University, Kohoku-ku, Yokohama, Japan;Faculty of Science and Technology Keio University, Kohoku-ku, Yokohama, Japan;Corporate Research and Development Center, Toshiba;Tokyo University of Agriculture and Technology;Faculty of Science and Technology Keio University, Kohoku-ku, Yokohama, Japan
Venue:
PDCN'07 Proceedings of the 25th conference on Proceedings of the 25th IASTED International Multi-Conference: parallel and distributed computing and networks
Year:
2007

Citing 10
Cited 1

Myrinet: A Gigabit-per-Second Local Area Network

IEEE Micro
The Quadrics Network: High-Performance Clustering Technology

IEEE Micro
Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot

PARELEC '02 Proceedings of the International Conference on Parallel Computing in Electrical Engineering
Performance Comparison of MPI Implementations over InfiniBand, Myrinet and Quadrics

Proceedings of the 2003 ACM/IEEE conference on Supercomputing
Evaluating InfiniBand Performance with PCI Express

IEEE Micro
Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board

PDCAT '05 Proceedings of the Sixth International Conference on Parallel and Distributed Computing Applications and Technologies
Preliminary Evaluation of a FPGA-Based-Prototype of DIMMnet-2 Network Interface

IWIA '05 Proceedings of the Innovative Architecture on Future Generation High-Performance Processors and Systems
Hardware Support for MPI in DIMMnet-2 Network Interface

IWIA '06 Proceedings of the International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems
Implementation and evaluation of the mechanisms for low latency communication on DIMMnet-2

ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
A preliminary analysis of the infinipath and XD1 network interfaces

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing

An enhancer of memory and network for applications with large-capacity data and non-continuous data accessing

The Journal of Supercomputing

Quantified Score

Hi-index	0.00

Visualization

Abstract

By recent performance improvement of interconnection networks for PC cluster, a standard I/O bus which connects network interface becomes the performance bottleneck. DIMMnet is a network interface which can solve the problem by using the memory bus instead of PCI bus or other I/O buses. The second generation network interface DIMMnet-2 can be connected with DDR-SDRAM slot. Although the current board is a prototype using an FPGA, using BOTF which is low latency PIO communication method, the bidirectional bandwidth reaches about 1087.56 MByte/s, and the minimum unidirectional latency is about 0.632 µs.