Hardware Support for MPI in DIMMnet-2 Network Interface

Authors:
Noboru Tanabe;Akira Kitamura;Tomotaka Miyashiro;Yasuo Miyabe;Takeshi Araki;Zhengzhe Luo;Hironori Nakajo;Hideharu Amano
Affiliations:
Toshiba;Keio University, Japan;Keio University, Japan;Keio University, Japan;Tokyo University of Agriculture and Technology, Japan;Tokyo University of Agriculture and Technology, Japan;Tokyo University of Agriculture and Technology, Japan;Keio University, Japan
Venue:
IWIA '06 Proceedings of the International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems
Year:
2006

Citing 0
Cited 2

Performance evaluation on low-latency Communication mechanism of DIMMnet-2

PDCN'07 Proceedings of the 25th conference on Proceedings of the 25th IASTED International Multi-Conference: parallel and distributed computing and networks
An enhancer of memory and network for applications with large-capacity data and non-continuous data accessing

The Journal of Supercomputing

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Abstract

In this paper, hardware support for MPI on the DIMMnet-2 network interface plugged into a DDR DIMM slot is presented. This hardware support realize effective eager protocol and effective derived datatype communication of MPI. As a preliminary evaluation, the evaluation results on the real prototype concerning the bandwidth of elements constituting MPI are shown. IPUSH, which is remote indirect writing, showed almost the same performance as RDMA, which is remote direct writing. IPUSH can reduce memory space required for a receiver buffer sharply. The memory space reduction effect of IPUSH on a system with more nodes is higher. Compared with a method that starts the burst vector loading many times, VLS, which performs a regular-interval vector loading, sharply accelerated access to the data arranged at regular intervals. The above-mentioned results indicate that the improvement in the speed of MPI by the proposed method is promising.