Development Brings Scalability to Hardware Evolution
EH '05 Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware
Generalized Disjunction Decomposition for the Evolution of Programmable Logic Array Structures
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Evolving multiplier circuits by training set and training vector partitioning
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Promises and challenges of evolvable hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
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Automatic design of electronic logic circuits has become a new research focus with the cooperation of FPGA technology and intelligent algorithms in recent twenty years. However, as the size of logic circuits became larger and more complex, it has become difficult for the automatic design method to obtain valid and optimized circuits. Based on a divide-and-conquer approach, a two-layer encoding scheme was devised for design of electronic logic circuits. In the process of evolvement, each layer was evolved parallel and they contacted each other at the same time. Moreover, in order to simulate and evaluate evolved electronic logic circuits, a two-step simulation algorithm was proposed to reduce computation complexity of simulating circuits and to improve the simulation efficiency. At last, a random number generator was automatically designed with this encoding scheme and the proposed simulation algorithm, and the result showed this method was efficient.