A model for intrinsic artificial development featuring structural feedback and emergent growth
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
Design of electronic circuits using a divide-and-conquer approach
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Introducing partitioning training set strategy to intrinsic incremental evolution
MICAI'06 Proceedings of the 5th Mexican international conference on Artificial Intelligence
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Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm. Evolvable hardware has shown one of its main deficiencies, when applied to solving real world applications, to be scalability. In the past few years several techniques have been proposed to avoid and/or solve this problem. Generalized disjunction decomposition (GDD) is one of these proposed methods. GDD was successful for the evolution of large combinational logic circuits based on a FPGA structure when used together with bi-directional incremental evolution and with (1+ë) evolution strategy. In this paper a modified generalized disjunction decomposition, together with a recently introduced multi-population genetic algorithm, are implemented and tested for its scalability for solving large combinational logic circuits based on Programmable Logic Array (PLA) structures.