A Scalable Approach to Evolvable Hardware
Genetic Programming and Evolvable Machines
Hardware Evolution at Function Level
PPSN IV Proceedings of the 4th International Conference on Parallel Problem Solving from Nature
MICAI '02 Proceedings of the Second Mexican International Conference on Artificial Intelligence: Advances in Artificial Intelligence
A Divide-and-Conquer Approach to Evolvable Hardware
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Evolutionary Design of Digital Circuits: Where Are Current Limits?
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Generalized Disjunction Decomposition for the Evolution of Programmable Logic Array Structures
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Artificial Life
Virtual reconfigurable circuits for real-world applications of evolvable hardware
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Evolving multiplier circuits by training set and training vector partitioning
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
CIS'05 Proceedings of the 2005 international conference on Computational Intelligence and Security - Volume Part I
Promises and challenges of evolvable hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
Real-world applications of analog and digital evolvable hardware
IEEE Transactions on Evolutionary Computation
FPGA Implementation of Evolvable Characters Recognizer with Self-adaptive Mutation Rates
ICANNGA '07 Proceedings of the 8th international conference on Adaptive and Natural Computing Algorithms, Part I
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In this paper, to conquer the scalability issue of evolvable hardware (EHW), we introduce a novel system-decomposition-strategy which realizes training set partition in the intrinsic evolution of a non-truth table based 32 characters classification system. The new method is expected to improve the convergence speed of the proposed evolvable system by compressing fitness value evaluation period which is often the most time-consuming part in an evolutionary algorithm (EA) run and reducing computational complexity of EA. By evolving target characters classification system in a complete FPGA-based experiment platform, this research investigates the influence of introducing partitioning training set technique to non-truth table based circuit evolution. The experimental results conclude that it is possible to evolve characters classification systems larger and faster than those evolved earlier, by employing our proposed scheme.