FPGA Implementation of Evolvable Characters Recognizer with Self-adaptive Mutation Rates

Authors:
Jin Wang;Chang Hao Piao;Chong Ho Lee
Affiliations:
Department of Information & Communication Engineering, Inha University, Incheon, Korea;Department of Automation Engineering, ChongQing University of Posts and Telecommunications, Chongqing, China;Department of Information & Communication Engineering, Inha University, Incheon, Korea
Venue:
ICANNGA '07 Proceedings of the 8th international conference on Adaptive and Natural Computing Algorithms, Part I
Year:
2007

Citing 10
Cited 0

A Scalable Approach to Evolvable Hardware

Genetic Programming and Evolvable Machines
A Pattern Recognition System Using Evolvable Hardware

PPSN IV Proceedings of the 4th International Conference on Parallel Problem Solving from Nature
Cartesian Genetic Programming

Proceedings of the European Conference on Genetic Programming
Bidirectional Incremental Evolution in Extrinsic Evolvable Hardware

EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Virtual reconfigurable circuits for real-world applications of evolvable hardware

ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Introducing partitioning training set strategy to intrinsic incremental evolution

MICAI'06 Proceedings of the 5th Mexican international conference on Artificial Intelligence
Using reconfigurable architecture-based intrinsic incremental evolution to evolve a character classification system

CIS'05 Proceedings of the 2005 international conference on Computational Intelligence and Security - Volume Part I
An evolvable image filter: experimental evaluation of a complete hardware implementation in FPGA

ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
Promises and challenges of evolvable hardware

IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
Parameter control in evolutionary algorithms

IEEE Transactions on Evolutionary Computation

Quantified Score

Hi-index	0.00

Visualization

Abstract

As an alternative to traditional artificial neural network approaches to pattern recognition, a hardware-implemented evolvable characters recognizer is presented in this paper. The main feature of the proposed evolvable system is that all the components including the evolutionary algorithm (EA), fitness calculation, and virtual reconfigurable circuit are implemented in a Xilinx Virtex xcv2000E FPGA. This allows for a completely pipelined hardware implementation and yields a significant speedup in the system evolution. In order to optimize the performance of the evolutionary algorithm and release the users from the time-consuming process of mutation parameters tuning, a self-adaptive mutation rate control scheme is also introduced. An analysis of experimental results demonstrates that the proposed evolvable system using self-adaptive mutation rates is superior to traditional fixed mutation rate-based approaches.