Dynamic partial reconfiguration in FPGAs

  • Authors:
  • Wang Lie;Wu Feng-yan

  • Affiliations:
  • Dept. of Computer Science & Electronic Information, Guangxi University, Nanning, China;Dept. of Computer Science & Electronic Information, Guangxi University, Nanning, China

  • Venue:
  • IITA'09 Proceedings of the 3rd international conference on Intelligent information technology application
  • Year:
  • 2009

Quantified Score

Hi-index 0.01

Visualization

Abstract

Dynamic parital reconfigurable FPGAs offer new design space with a variety of benefits: reduce the configuration time and save memory as the partial reconfiguration files (bitstreams) are smaller than full ones. This paper introduces a simple reconfigurable system and focuses on the advantages of the newest dynamic partial reconfiguration design flow.