Analog Integrated Circuits and Signal Processing
Radio Design in Nanometer Technologies
Radio Design in Nanometer Technologies
Integration, the VLSI Journal
IEEE Wireless Communications
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This paper describes the design and experimental characterization of a 0.13@mm CMOS switched-capacitor reconfigurable cascade @S@D modulator intended for multi-standard GSM/Bluetooth/UMTS hand-held devices. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt the effective resolution and the output rate to different standard specifications with optimized power dissipation. This is achieved by properly combining different reconfiguration modes that include the variation in the order of the loop filter (3rd- or 4th-order), the clock frequency (40 or 80MHz), the internal quantization (1 or 2bits), and the bias currents of the amplifiers. The selection of the modulator topology and the design of its building blocks are based on a top-down CAD methodology that combines simulation and statistical optimization at different levels of the modulator hierarchy. Experimental measurements show a correct operation of the prototype for the three standards, featuring dynamic ranges of 83.8/75.9/58.7dB and peak signal-to-(noise+distortion) ratios of 78.7/71.3/53.7dB at 400ksps/2/8Msps, respectively. The modulator power consumption is 23.9/24.5/44.5mW, of which 9.7/10/24.8mW are dissipated in the analog circuitry. The multi-mode @S@D prototype shows an overall performance that is competitive with the current state of the art.