Bandpass delta-sigma data converters
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
A triple-mode reconfigurable sigma-delta modulator for multi-standard wireless applications
Proceedings of the conference on Design, automation and test in Europe
Reconfigurable multi-mode sigma-delta modulator for 4G mobile terminals
Integration, the VLSI Journal
Adaptive CMOS analog circuits for 4G mobile terminals-Review and state-of-the-art survey
Microelectronics Journal
A 0.13µm CMOS adaptive sigma-delta modulator for triple-mode GSM/Bluetooth/UMTS applications
Microelectronics Journal
Hi-index | 0.00 |
This paper represents the low-power signal-delta (驴驴) modulator for wireless communication receiver applications. The 2nd-order modulator has a single-loop structure with 11 quantization levels. An adaptive biasing scheme of the operational amplifier and cascaded comparator scheme are proposed in order to save the power consumption. The DAC with three-level references including the analog ground voltage can make the modulator be implemented with half of the input capacitances without degradation of linearity characteristics with the help of dynamic element matching technique. Peak SNR values of 74 dB and 68 dB are achieved with the input bandwidths of 615 kHz and 1.92 MHz for CDMA-2000 and WCDMA applications, respectively. The modulator is fabricated in a 0.13-驴m standard digital CMOS technology and dissipates 4.3 mA for a single supply voltage of 2.8 V.