FPGA implementation of genetic vector quantizers

Authors:
Chien-Min Ou
Affiliations:
Department of Electronics Engineering, Ching-Yun University, Chungli 320, Taiwan
Venue:
Neurocomputing
Year:
2010

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Abstract

This paper presents a novel hardware architecture for genetic vector quantizer (VQ) design. It is based on steady-state genetic algorithm (GA) and adopts shift registers for accelerating mutation and crossover operations while reducing area cost. It also uses a pipeline for fitness evaluation. The proposed architecture has been embedded in a softcore CPU for physical performance measurement. Experimental results show that it is an effective alternative for VQ optimization attaining both high performance and low computational time.