LIRS-WSR: integration of LIRS and writes sequence reordering for flash memory

  • Authors:

  • Hoyoung Jung;Kyunghoon Yoon;Hyoki Shim;Sungmin Park;Sooyong Kang;Jaehyuk Cha

  • Affiliations:

  • Dept. of Electronics and Computer Engineering, Hanyang Univ., Seoul, Korea;Dept. of Electronics and Computer Engineering, Hanyang Univ., Seoul, Korea;Dept. of Electronics and Computer Engineering, Hanyang Univ., Seoul, Korea;Dept. of Electronics and Computer Engineering, Hanyang Univ., Seoul, Korea;Dept. of Computer Science Education, Seoul, Korea;Dept. of Informations and Communications, Hanyang Univ., Seoul, Korea

  • Venue:
  • ICCSA'07 Proceedings of the 2007 international conference on Computational science and its applications - Volume Part I
  • Year:
  • 2007

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Abstract

Most of the mobile devices are equipped with NAND flash memories even if it has characteristics of not-in-place update and asymmetric I/O latencies among read, write, and erase operations: a write/erase operation is much slower than a read operation in a flash memory. For the overall performance of a flash memory system, the buffer replacement policy should consider the above severely asymmetric I/O latencies. Existing buffer replacement algorithms such as LRU, LIRS, and ARC cannot deal with the above problems. This paper proposes an add-on buffer replacement policy that enhances LIRS by reordering writes of not-cold dirty pages from the buffer cache to flash storage. The enhances LIRS-WSR algorithm focuses on reducing the number of write/erase operations as well as preventing serious degradation of buffer hit ratio. The trace-driven simulation results show that, among the existing buffer replacement algorithms including LRU, CF-LRU, ARC, and LIRS, our LIRSWSR is best in almost cases for flash storage systems.