The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The future of multiprocessor systems-on-chips
Proceedings of the 41st annual Design Automation Conference
An efficient system-on-a-chip design methodology for networking applications
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Design trade-offs and power reduction techniques for high performance circuits and system
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part V
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This paper discusses a large number of logic circuit mapping methods for complex systems, focusing on network hardware system designs. This logic mapping technique enables significant logic simulation time savings by mapping identical logic processor modules. Under the logic mapping method which is called the time division multiplexing (TDM) logic mapping method, the speed of the required to simulate it is significantly reduced, compared with conventional mapping methods, when folding the identical modules into a single module copy is done at the hardware description language (HDL) level. In principle, this method can be applied to any type of a network design platform, e.g., communication data stream through physical channel (fiber optic line), video signal transfer logic display environment, etc. In this paper, we demonstrate this method using several configurations of the IBM Serial Link architecture.