Design trade-offs and power reduction techniques for high performance circuits and system

Authors:
Taikyeong T. Jeong;Anthony P. Ambler
Affiliations:
Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX;Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX
Venue:
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part V
Year:
2006

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ICCSA'07 Proceedings of the 2007 international conference on Computational science and its applications - Volume Part I

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Abstract

This paper presents a novel low power design methodology for dynamic CMOS circuits in order to improve the design trade-off between power and speed. It also discusses a new design methodology of power reduction techniques for high-performance chips. As confirmed through the experiment, we are maximizing the performance of the chip in terms of speed and power. The simulation results of the proposed method are compared and possible improvements and applications are discussed.