Limits for automatic verification of finite-state concurrent systems
Information Processing Letters
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The temporal logic of reactive and concurrent systems
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ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
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Journal of the ACM (JACM)
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ACM Transactions on Programming Languages and Systems (TOPLAS)
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POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
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ACM Transactions on Programming Languages and Systems (TOPLAS)
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LICS '02 Proceedings of the 17th Annual IEEE Symposium on Logic in Computer Science
Automatic Deductive Verification with Invisible Invariants
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
TVLA: A System for Implementing Static Analyses
SAS '00 Proceedings of the 7th International Symposium on Static Analysis
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CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
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Proceedings of the twenty-second annual symposium on Principles of distributed computing
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Science of Computer Programming
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FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
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Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
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Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
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Proceedings of the 2009 ACM SIGPLAN conference on Programming language design and implementation
Invariant synthesis for combined theories
VMCAI'07 Proceedings of the 8th international conference on Verification, model checking, and abstract interpretation
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
DISC'06 Proceedings of the 20th international conference on Distributed Computing
A framework for formally verifying software transactional memory algorithms
CONCUR'12 Proceedings of the 23rd international conference on Concurrency Theory
Verifying concurrent programs against sequential specifications
ESOP'13 Proceedings of the 22nd European conference on Programming Languages and Systems
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We describe an automatic verification method to check whether transactional memories ensure strict serializability a key property assumed of the transactional interface. Our main contribution is a technique for effectively verifying parameterized systems. The technique merges ideas from parameterized hardware and protocol verification--verification by invisible invariants and symmetry reduction--with ideas from software verification--template-based invariant generation and satisfiability checking for quantified formulæ (modulo theories). The combination enables us to precisely model and analyze unbounded systems while taming state explosion. Our technique enables automated proofs that two-phase locking (TPL), dynamic software transactional memory (DSTM), and transactional locking II (TL2) systems ensure strict serializability. The verification is challenging since the systems are unbounded in several dimensions: the number and length of concurrently executing transactions, and the size of the shared memory they access, have no finite limit. In contrast, state-of-the-art software model checking tools such as BLAST and TVLA are unable to validate either system, due to inherent expressiveness limitations or state explosion.