An introduction to ray tracing
An introduction to ray tracing
ARTS: accelerated ray-tracing system
Tutorial: computer graphics; image synthesis
Illumination for computer generated pictures
Seminal graphics
Realistic ray tracing
An improved illumination model for shaded display
Communications of the ACM
On the efficiency of ray-shooting acceleration schemes
SCCG '02 Proceedings of the 18th spring conference on Computer graphics
Realtime ray tracing of dynamic scenes on an FPGA chip
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
RPU: a programmable ray processing unit for realtime ray tracing
ACM SIGGRAPH 2005 Papers
Distributed Interactive Ray Tracing of Dynamic Scenes
PVG '03 Proceedings of the 2003 IEEE Symposium on Parallel and Large-Data Visualization and Graphics
Ray tracing on programmable graphics hardware
SIGGRAPH '05 ACM SIGGRAPH 2005 Courses
Ray Tracing from the Ground Up
Ray Tracing from the Ground Up
GridRT: A Massively Parallel Architecture for Ray-Tracing Using Uniform Grids
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
An efficient parallel architecture for ray-tracing
Analog Integrated Circuits and Signal Processing
Journal of Systems Architecture: the EUROMICRO Journal
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Real time performance of non-interactive rendering of three-dimensional scenes is usually unachievable. Ray tracing is one of the methods used for rendering such scenes. The performance achieved by a sequential software-based implementation of ray tracing is far from satisfactory. In contrast, many parallel implementations of ray tracing have been enabling real time performance, as the underlying algorithm can be massively parallelised. Thus, it is expected that a custom parallel design in hardware is likely to achieve the acceptable performance standards. In this paper, we propose a hardware architecture, which we call GridRT, capable of dealing with the main desirable features of ray tracing, such as shadows and reflections effects, imposing low requirements in terms of silicon area while achieving acceptable performance in terms of rendering time. This architecture achieves is efficient yet compact as it explores the massive parallelism offered by the intrinsic structure of the algorithm. The design exploits the usage the spatial data structure of regular grids.