Journal of VLSI Signal Processing Systems
Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies
Journal of VLSI Signal Processing Systems
Design of RNS-based distributed arithmetic DWT filterbanks
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
Efficient sample rate conversion in software radio employing folding number system
ICC'09 Proceedings of the 2009 IEEE international conference on Communications
Use of the symmetrical number system in resolving single-frequencyundersampling aliases
IEEE Transactions on Signal Processing
Adder based residue to binary number converters for(2n-1, 2n, 2n+1)
IEEE Transactions on Signal Processing
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In this paper, a new architecture to compute 1-D Discrete Wavelet Transform (DWT) based on Folding Number System (FNS) is introduced. Numbers for FNS are extracted directly from analog input without any forward converter like in the Residue Number System (RNS) based DWT. The large Dynamic Range makes the FNS DWT more efficient than those implemented using RNS systems. The proposed 1- D DWT architecture makes use of the relation between the coefficients of the low-pass and high-pass decomposition filters for orthogonal wavelets families to compute the transform with minimum numbers of modular multipliers. These multipliers are based on pipelined Look-Up Tables (LUT). A 6-tap Daubechies analysis filter bank is synthesized at a structural level using VHDL. FLEX10K devices of Altera are used in the simulation of DWT using binary arithmetic, RNS and FNS to evaluate its performance. Simulations show a significant throughput improvement is achieved in the proposed FNS DWT architecture when {2k - 1, 2k, 2k + 1} moduli set is used.