Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An adaptively biased low-dropout regulator with transient enhancement
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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A high-precision low-voltage adaptively biased (AB) low-dropout regulator (LDR) with extended loop bandwidth is proposed. The multistage output-capacitor-free LDR is stabilized by Miller compensation and Q-reduction techniques to reduce the required minimum load current. Adaptive biasing is achieved by using direct current feedback from a simple current mirror. The dynamics of both the main feedback loop (MFL) and the adaptive biasing loop are thoroughly analyzed. Tradeoffs between the adaptive biasing factor and the MFL stability are discussed. The AB LDR is designed using a standard 0.35- µm CMOS technology (Vtn ≈ 0.52 V and tp ≈ -0.72 V). The output is 1.0 V, which delivers a maximum current of 100 mA. The minimum input voltage is 1.2 V, and the minimum load current required is reduced to 50 µA. Extensive simulation results verify that the proposed LDR achieves high loop bandwidth, fast line and load transient responses, high power supply rejection, and low output impedance.