Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
Output-capacitor-free adaptively biased low-dropout regulator for system-on-chips
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS 2009
A chip-area efficient voltage regulator for VLSI systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An adaptively biased low-dropout regulator with transient enhancement
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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A capacitor-less low dropout regulator (LDR) with direct current feedback is proposed. A symmetrically-matched voltage mirror in sensing the load current is employed, and gives excellent line and load regulations. The dynamic biasing results in an LDR with pole-tracking that extends the bandwidth of the loop gain at high load currents. The LDR was fabricated in a 0.35μm CMOS process with an active area of 0.11mm2, and measurement results corroborated well with both analysis and simulation.