Switching Activity Minimization in Iterative LDPC Decoders
Journal of Signal Processing Systems
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Stochastic iterative decoders are a recently introduced hardware-oriented class of message-passing algorithms for ultra-low complexity error-correcting decoders. We show that dynamic power consumption in stochastic decoders is exposed at the algorithmic level and can be evaluated from the values of messages passed on the code’s factor graph. This observation leads to a method for evaluating the relative dynamic power consumption of stochastic decoders as early as the code design stage. We propose a method based on density evolution that can be used to compare code ensembles in terms of their decoding energy per information bit. We note that despite using a stochastic signaling scheme, stochastic decoders converge to a codeword and stop consuming dynamic power. Results illustrate that significant differences in power consumption can be identified at the code design stage and tradeoffs can be exploited before designing a specific implementation.