An area-efficient maximum-ratio-combining diversity receiver in 90 nm CMOS for free-space optical links

Authors:
V. M. Joyner;Y. Zhang;J. Zeng
Affiliations:
Department of Electrical and Computer Engineering, Tufts University, Medford, USA 02155;Department of Electrical and Computer Engineering, Tufts University, Medford, USA 02155;Department of Electrical and Computer Engineering, Tufts University, Medford, USA 02155
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2010

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Abstract

This paper presents a low-power imaging diversity front-end receiver employing the maximum-ratio-combining algorithm for free-space optical communication. It consists of seven signal channels and an output stage, each channel has a front-end transimpedance amplifier, a signal-to-noise ratio (SNR) estimator and a variable gain amplifier (VGA). The imaging receiver circuit was implemented in a 90 nm CMOS process. The maximum-ratio weighting is achieved with the SNR estimator and variable gain amplifier (VGA), which provides the signal with a gain proportional to the signal amplitude. The maximum ratio combining feature was demonstrated with two channels driven by photodiode emulation circuits for electrical characterization. The power dissipation for the whole chip is 43 mW from a single 1.2 V supply.