An ultra-low power successive approximation A/D converter with time---domain comparator

Authors:
Andrea Agnes;Edoardo Bonizzoni;Piero Malcovati;Franco Maloberti
Affiliations:
Department of Electronics, University of Pavia, Pavia, Italy 27100;Department of Electronics, University of Pavia, Pavia, Italy 27100;Department of Electrical Engineering, University of Pavia, Pavia, Italy 27100;Department of Electronics, University of Pavia, Pavia, Italy 27100
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2010

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Abstract

This paper presents an ultra-low power successive approximation analog-to-digital converter. An improved implementation of the binary weighted capacitors array and a novel comparator that operates in the time instead of the voltage domain are effective and power efficient. The circuit, fabricated in a conventional 0.18-μm CMOS technology, achieves a sampling rate of 100 kS/s and an effective number of bit of 9.4. Using a 1-V supply voltage, the achieved power consumption is 3.8 μW, leading to a Figure of Merit as low as 56 fJ/conversion-level.