Design and analysis of a robust pipelined memory system

Authors:
Hao Wang;Haiquan Zhao;Bill Lin;Jun Xu
Affiliations:
Department of Electrical and Computer Engineering, University of California, San Diego;College of Computing, Georgia Institute of Technology;Department of Electrical and Computer Engineering, University of California, San Diego;College of Computing, Georgia Institute of Technology
Venue:
INFOCOM'10 Proceedings of the 29th conference on Information communications
Year:
2010

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Abstract

Many network processing applications require wirespeed access to large data structures or a large amount of flowlevel data, but the capacity of SRAMs is woefully inadequate in many cases. In this paper, we analyze a robust pipelined memory architecture that can emulate an ideal SRAM by guaranteeing with very high probability that the output sequence produced by the pipelined memory architecture is the same as the one produced by an ideal SRAM under the same sequence of memory read and write operations, except time-shifted by a fixed pipeline delay of Δ. The design is based on the interleaving of DRAM banks together with the use of a reservation table that serves in part as a data cache. In contrast to prior interleaved memory solutions, our design is robust even under adversarial memory access patterns, which we demonstrate through a rigorous worstcase theoretical analysis using a combination of convex ordering and large deviation theory.