Virtually Pipelined Network Memory
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Designing packet buffers for router linecards
IEEE/ACM Transactions on Networking (TON)
High-bandwidth network memory system through virtual pipelines
IEEE/ACM Transactions on Networking (TON)
Design and analysis of a robust pipelined memory system
INFOCOM'10 Proceedings of the 29th conference on Information communications
A novel hybrid SRAM/DRAM memory architecture for fast packet buffers
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
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High performance routers require substantial amounts of memory to store packets awaiting transmission, requiring the use of dedicated memory devices with the density and capacity to provide the required storage economically. The memory bandwidth required for packet storage subsystems often exceeds the bandwidth of individual memory devices, making it necessary to implement packet storage using multiple memory channels. This raises the question of how to design multichannel storage systems that make effective use of the available memory and memory bandwidth, while forwarding packets at link rate in the presence of arbitrary packet retrieval patterns. A recent series of papers has demonstrated an architecture that uses on-chip SRAM to buffer packets going to/from a multi-channel storage system, while maintaining high performance in the presence worst-case traffic patterns. Unfortunately, the amount of on-chip storage required grows as the product of the number of channels and the number of separate queues served by the packet storage system. This makes it too expensive to use in systems with large numbers of queues. We show how to design a practical randomized packet storage system that can sustain high performance using an amount of on-chip storage that is independent of the number of queues.