Verification of digital circuits based on formal semantics of a hardware description language

Graph-Based Algorithms for Boolean Function Manipulation

IEEE Transactions on Computers

A computational logic handbook

A computational logic handbook

Automatic Verification of Extensions of Hardware Descriptions

CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification

Using Partial-Order Semantics to Avoid the State Explosion Problem in Asynchronous Systems

CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification

Using the HOL Prove Assistant for proving the Correctness of term Rewriting Rules reducing Terms of Sequential Behavior

CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification

Mechanizing a Proof by Induction of Process Algebrs Specifications in Higher Order Logic

CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification