Optimization of a multi-Constant Work-in-Process semiconductor assembly and test factory based on performance evaluation

  • Authors:

  • Na Li;Shiqing Yao;George Liu;Caihua Zhuang

  • Affiliations:

  • Department of Industrial Engineering, Shanghai Jiao Tong University, Shanghai, China;Department of Industrial Engineering, Shanghai Jiao Tong University, Shanghai, China;Solver Solution Engineering Team, Intel Corporation, No. 8-1, Kexin Road, Chengdu High-Tech Zone (West Park), Chengdu, Sichuan, China;Department of Industrial Engineering, Shanghai Jiao Tong University, Shanghai, China

  • Venue:
  • Computers and Industrial Engineering
  • Year:
  • 2010

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Abstract

This paper considers a semiconductor assembly and test factory which is a three-segment-Constant Work-in-Process (CONWIP) system with overlapping machines. In the system, three types of carts circulate for meeting the physical requirements. The optimization problem in setting the suitable total Work-in-Process (WIP) level and the distribution in the three loops from the view of the trade-off between the throughput and the WIP level for the system is addressed. In the proposed model, the system is firstly modeled as a three-loop closed queue network and we propose an approximate method to evaluate the performance. The accuracy of the evaluation method was illustrated by numerical experiments, indicating that the method is fairly precise. Secondly, a Genetic Algorithm is designed to obtain near optimal results based on the performance evaluation. The semiconductor assembly and test system case as well as the application procedure were carried out in detail.