A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter

Authors:
Roberto Perez-Andrade;René Cumplido;Claudia Feregrino-Uribe;Fernando Martin Del Campo
Affiliations:
Department of Computer Science, National Institute for Astrophysics, Optics and Electronics, Puebla, Mexico;Department of Computer Science, National Institute for Astrophysics, Optics and Electronics, Puebla, Mexico;Department of Computer Science, National Institute for Astrophysics, Optics and Electronics, Puebla, Mexico;Department of Computer Science, National Institute for Astrophysics, Optics and Electronics, Puebla, Mexico
Venue:
Digital Signal Processing
Year:
2010

Citing 3
Cited 0

VLSI architectures for CFAR detectors based on order statistics

Signal Processing
Adaptive CFAR PI Processor for Radar Target Detection in Pulse Jamming

Journal of VLSI Signal Processing Systems
A versatile linear insertion sorter based on an FIFO scheme

Microelectronics Journal

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Abstract

Constant False Alarm Rate (CFAR) algorithms are used in digital signal processing applications to extract targets from background in noisy environments. Some examples of applications are target detection in radar environments, image processing, medical engineering, power quality analysis, features detection in satellite images, Pseudo-Noise (PN) code detectors, among others. This paper presents a versatile hardware architecture that implements six variants of the CFAR algorithm based on linear and nonlinear operations for radar applications. Since some implemented CFAR algorithms require sorting the input samples, a linear sorter based on a First In First Out (FIFO) schema is used. The proposed architecture, known as CFAR processor, can be used as a specialized module or co-processor for Software Defined Radar (SDR) applications. The results of implementing the CFAR processor on a Field Programmable Gate Array (FPGA) are presented and discussed.