Introduction to algorithms
Matrix Computations on Systolic-Type Arrays
Matrix Computations on Systolic-Type Arrays
Digital Quadrature Demodulation of LFM Signals Obtained by Lowpass Filtering
NMA '02 Revised Papers from the 5th International Conference on Numerical Methods and Applications
CFAR Processors in Pulse Jamming
NMA '02 Revised Papers from the 5th International Conference on Numerical Methods and Applications
Systolic architecture for adaptive censoring CFAR PI detector
LSSC'05 Proceedings of the 5th international conference on Large-Scale Scientific Computing
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A new parallel algorithm for signal processing and a parallel systolic architecture of a CFAR processor with adaptive post detection integration (API) are presented in this paper. The processor proposed is used for effective target detection in a single range resolution cell of a radar when echoes from small airborne targets are performed in conditions of pulse jamming. The main property of the algorithm proposed is its ability automatically to determine and censor the unwanted samples corrupted by pulse jamming in both the two-dimensional reference window and the test cell before noise level estimation. In such a way the influence of pulse jamming environment over adaptive thresholding is reduced to minimum. Statistical analysis of the algorithm for target detection shows that the signal-to-noise ratio losses are insignificant even if the power and the frequency of pulse jamming are extremely high. The systolic architecture of the CFAR API is designed. Basic measures of the systolic architecture are the number of processor elements, the computational time and the speed-up needed for real-time implementation.