Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
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The design of an integrated lock-in amplifier is discussed, specifically conceived for the detection of low-level signals at a harmonic of the drive frequency in magnetically excited resonant structures. The circuit includes in-phase and quadrature analogue signal processing channels, whose outputs feed an integrated @S@D analogue to digital converter. The circuit can be operated in different configurations, depending on the application requirements: in particular, by combining the digitized outputs of the two channels, vector operation can be obtained. The entire analogue chain, including the @S@D modulator, was designed using fully differential elaboration. The circuit was developed in a 0.35@mm, dual poly-Si, four metal layers analogue CMOS technology with high resistivity poly-Si option. Circuit performance is discussed on the basis of transistor-level simulations and measurement results.