High-throughput layered decoder implementation for quasi-cyclic LDPC codes
IEEE Journal on Selected Areas in Communications - Special issue on capaciyy approaching codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Structured puncturing for rate-compatible B-LDPC codes with dual-diagonal parity structure
IEEE Transactions on Wireless Communications
Quasi-cyclic LDPC codes for fast encoding
IEEE Transactions on Information Theory
Rate-compatible punctured low-density parity-check codes with short block lengths
IEEE Transactions on Information Theory
Low-complexity reliability-based message-passing decoder architectures for non-binary LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present a rate-compatible LDPC decoder architecture which supports code rates between the rate of the mother code and 1. The rate-1/2 2304-bit Quasi-Cyclic (QC) LDPC codes with dual-diagonal parity check structure is selected from WiMax standard as the mother code and is punctured using specific puncturing patterns to obtain arbitrary rates. Parallel layered decoding architecture (PLDA) is employed to reduce chip area and improve the throughput. Simulation results show that the proposed punctured codes have comparable error correcting performances with the performances of dedicated codes from WiMax standard. The decoder is implemented on the platform of Xilinx XC2V8000. Compared with previous WiMax LDPC decoders synthesized by the same device, our low-complexity decoder consumes less FPGA resources: reduction of slices by 63%, flip-flops by 73%, look-up tables (LUTs) by 60% and RAMs by 30%.