Reducing computation overhead of flash translation layer with hash

Authors:
Ilhoon Shin
Affiliations:
Department of Electronics and Information Engineering, Seoul National University of Technology, Seoul, South Korea
Venue:
ACACOS'10 Proceedings of the 9th WSEAS international conference on Applied computer and applied computational science
Year:
2010

Citing 3
Cited 0

A Re-configurable FTL (Flash Translation Layer) Architecture for NAND Flash based Applications

RSP '07 Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping
A log buffer-based flash translation layer using fully-associative sector translation

ACM Transactions on Embedded Computing Systems (TECS)
A space-efficient flash translation layer for CompactFlash systems

IEEE Transactions on Consumer Electronics

Quantified Score

Hi-index	0.00

Visualization

Abstract

NAND flash memory does not support the overwrite operation and thus it deploys the flash translation layer which performs the out-place update. When designing a flash translation layer, memory consumption, computation complexity, and garbage collection overhead should be low. However, the representative sector mapping scheme of flash translation layer, FAST causes a huge computation complexity even though it minimizes the memory consumption and the garbage collection overhead. This paper presents a hashed page table for the FAST scheme to reduce the computation overhead. The simulation result shows that the presented method contributes to reduce the computation overhead considerably.