The design of fast-settling three-stage amplifiers using the open-loop damping factor as a design parameter

Authors:
Ray Nguyen;Boris Murmann
Affiliations:
Department of Electrical Engineering, Stanford University, Stanford, CA;Department of Electrical Engineering, Stanford University, Stanford, CA
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2010

Citing 3
Cited 0

Analysis and Design of Analog Integrated Circuits

Analysis and Design of Analog Integrated Circuits
Single Miller capacitor frequency compensation with nulling resistor for three-stage amplifiers

International Journal of Circuit Theory and Applications
Settling time minimization of operational amplifiers

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents an open-loop design method for fast-settling three-stage class-A amplifiers. Specifically, using the open-loop damping factor as a design parameter, the presented method delivers robust settling performance of a third-order system in the presence of process and component variation. As an illustration of the proposed approach, we show Spice simulation results of a nested-Miller-compensated three-stage-amplifier designed in 0.35-µm CMOS technology. The design achieves a 1 % and 0.1 % dynamic-error settling times of 6.4 ns and 13.7 ns, respectively, at a gain-bandwidth product of 55 MHz and a dynamic range of 80 dB, while consuming 5.4 m W from a 3-V supply.