A multilevel algorithm for partitioning graphs
Supercomputing '95 Proceedings of the 1995 ACM/IEEE conference on Supercomputing
Multilevel k-way partitioning scheme for irregular graphs
Journal of Parallel and Distributed Computing
A new partitioning method for parallel simulation of VLSI circuits on transistor level
DATE '00 Proceedings of the conference on Design, automation and test in Europe
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In coarse-grained parallelism, it is effective to partition the network into Bordered Block Diagonal Form (BBDF) before subsequent parallel computation. An implementation of parallel power flow calculation based on a novel graph partitioning algorithm, which transforms the admittance matrix into nested BBDF (NBBDF), is presented in this paper. In order to avoid excessive fill-ins during Gaussian elimination, a vertex ordering scheme is discussed. Distributed file storage combined with task scheduling is proposed for improving parallel efficiency. Testing results for grids with up to 5317 buses indicate that this proposed method is able to bring superlinearity into parallel power flow calculation for large-scale power systems.