Design methodology using inversion coefficient for low-voltage low-power CMOS voltage reference

  • Authors:

  • Dalton Martini Colombo;Gilson Inacio Wirth;Christian Fayomi

  • Affiliations:

  • UFRGS, Porto Alegre, Brazil;UFRGS, Porto Alegre, Brazil;UQAM, Montreal, PQ, Canada

  • Venue:
  • SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
  • Year:
  • 2010

Quantified Score

Hi-index 0.00

Visualization

Abstract

This paper presents an analog design methodology, using the selection of inversion coefficient of MOS devices, to design low voltage and low-power (LVLP) CMOS voltage references. These circuits often work under subthreshold operation. Hence, there is a demand for analog design methods that optimize the sizing process of transistors working in weak and moderate inversion. The advantage of the presented method -- compared with the traditional approach to design circuits -- is the reduction of design cycle time and minimization of trial-and-error simulations, if the proposed equations are used. As a case study, a LVLP voltage reference based on subthreshold MOSFETs with supply voltage of 0.7 V was designed for 0.18-¼m CMOS technology.