An all-digital phase-locked loop with high resolution for local on-chip clock synthesis
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
An integrated 10 GHz low-noise phase-locked loop with improved PVT tolerance
Analog Integrated Circuits and Signal Processing
Analysis and minimization of substrate spurs in fractional-N frequency synthesizers
Analog Integrated Circuits and Signal Processing
| Hi-index | 0.00 |
We present an integrated fractional-N low-noise frequency synthesizer for satellite applications. By using two integrated VCOs and combining digital and analog tuning techniques, a PLL lock range from 8 to 12 GHz is achieved. Due to a small VCO fine tuning gain and optimized charge pump output biasing, the phase noise is low and almost constant over the tuning range. All 16 sub-bands show a tuning range above 900 MHz each, allowing temperature compensation without sub-band switching. This makes the synthesizer robust against variations of the device parameters with process, supply voltage, temperature and aging. The measured phase noise is 驴87 dBc/Hz and 驴106 dBc/Hz at 10 kHz and 1 MHz offset, respectively. In integer-N mode, phase noise values down to 驴98 dBc/Hz at 10 kHz and 驴111 dBc/Hz at 1 MHz offset, respectively, were measured.