RF microelectronics
A 2.5 V, 10 GHz Fully Integrated LC-VCO with Integrated High-Q Inductor and 30% Tuning Range
Analog Integrated Circuits and Signal Processing
An analytical phase noise model of charge pump mismatch in sigma-delta frequency synthesizer
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing
Analytical phase-noise modeling and charge pump optimization for fractional-N PLLs
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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An integrated phase-locked loop (PLL) with low phase noise is presented, which is robust with respect to variations of device parameters with process, supply voltage, and temperature (PVT). The low-noise CMOS voltage-controlled oscillator (VCO) employs two varactors for fine and coarse tuning. By using a CMOS charge pump with output biasing, the dc fine tuning voltage of the VCO and the loop dynamics of the PLL are well defined and fairly independent of PVT variations. Device noise in the charge pump and linearity of the phase detector are much improved by a two-transistor charge pump architecture for fine tuning. We measured a phase noise below 驴131 dBc/Hz at 10 MHz offset and below 驴94 dBc/Hz at 10 kHz offset over a tuning range of 1.2 GHz. An integrated phase error below 0.6° was measured, corresponding to an rms jitter below 160 fs. The chip was produced in a 0.25 μm low-cost SiGe BiCMOS technology, occupies a chip area of 2.25 mm2 and draws 60 mA from a 3 V supply.