Optimal ΣΔ modulator architectures for fractional-N frequency synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analytical phase-noise modeling and charge pump optimization for fractional-N PLLs
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Multimode reconfigurable digital ΣΔ modulator architecture for fractional-N PLLs
IEEE Transactions on Circuits and Systems II: Express Briefs
An integrated 10 GHz low-noise phase-locked loop with improved PVT tolerance
Analog Integrated Circuits and Signal Processing
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Although some papers have qualitatively analyzed the effect of charge pump mismatch on phase noise and spurs in sigma-delta fractional-N frequency synthesizer, few of them have addressed this topic quantitatively. An analytical model is proposed in this paper to describe the behavior of charge pump mismatch and the corresponding phase noise. Numerical simulation shows that this model is of high accuracy and can be applied to the analysis of in-band phase induced by the charge pump mismatch in sigma-delta fractional-N PLL frequency synthesizer. Most importantly, this model discloses that 6 dB reduction of in-band phase noise due to charge pump mismatch can be achieved by halving the charge pump mismatch ratio. After studying the typical topologies of sigma-delta modulators (SDM), we proposed some strategies on the selection of SDM in frequency synthesizer design. Our analytical model also indicates that eliminating the charge pump mismatch is one major path towards the in-band phase noise reduction of the sigma-delta frequency synthesizer.